DDC-I, a leading supplier of software and professional services for mission- and safety-critical applications, announced that it has completed multicore DO-178C verification to Design Assurance Level A (DAL A) for its Deos DO-178C safety-critical real-time operating system (RTOS) on multiple ARM and PowerPC processors. Deos now provides an off-the-shelf set of DAL-A artifacts for a broad range of ARM and PowerPC multicore processors, including the PowerPC e6500 core and the ARM-based Xilinx Zynq Ultrascale+ MPSoC, NXP QorIQ, Layerscape, S32 (automotive), and iMX processor families. This is the second verified baseline of DDC-I’s multicore kernel technology to DO-178C DAL-A. Verification for Intel’s I7 Tiger Lake and Texas Instruments’ Jacinto are planned for release in the next verified baseline.
“DDC-I has been at the forefront of DO-178C multicore technology development, standardization and verification, with an emphasis on satisfying the CAST-32A and AMC 20-193 objectives for safety-critical operation,” said Greg Rose, vice president of marketing at DDC-I. “Further, Deos takes a different approach to multicore processing versus other certifiable RTOSs by providing technology to reduce cross core interference rather than relying on draconian safety nets as the primary bounding mechanism. Our unique multicore features enable our customers to achieve the highest level of safety-critical operation in the gamut of avionics applications from highly deterministic FADECs and flight controls, to complex high throughput displays and mission computers.”
Deos is a safety-critical embedded RTOS that uses patented technology to deliver the highest possible CPU utilization on multi-core processors. First certified to DO-178 DAL A in 1998, Deos features hard real-time response, time and space partitioning, ARINC-653 and POSIX interfaces and conformance to the FACE™ technical specification v3.1 for the Safety Extended and Safety Base Profiles. With an emphasis on safety-critical multicore applications, Deos scales well for all compute- and I/O intensive avionics applications such as those requiring data fusion, and other advanced control and sensor functionality.
DDC-I’s SafeMC technology extends Deos’ advanced capabilities to multiple cores, enabling developers of safety-critical systems to achieve best in class multicore performance without compromising safety-critical task response and guaranteed execution time. SafeMC employs a bound multiprocessing (BMP) architecture, safe scheduling, and cache partitioning to minimize cross-core contention and interference patterns that affect the performance, safety and certifiability of multi-core systems. The patented cache partitioning technology is unique to Deos and enables L2/L3 cache segregation at a per-application level. This feature bounds cache jitter to dramatically improve worse-case execution times. Then as a final line of defense against run-bound operation, customers can employ the safety nets of bandwidth restriction for resource over utilization, which protects against catastrophic error conditions. These features enable avionics system developers to address issues that could impact the integrity, safety, performance, and the burden associated with the certification of a multi-core airborne system.